1. Field of the Invention
The present invention relates to a display apparatus, such as a liquid crystal display (LCD) device, a plasma display device, a field emission display device, with a high response speed which can prevent the display image from becoming unclear due to an overlap of the afterimage of the display image of the preceding frame period with the display image of the current frame period to improve the image quality of the motion picture.
2. Discussion of the Related Art
The LCD device with the high response speed, such as a Bend-mode LCD device well known in the art, has been used for improving the image quality of the motion picture in which the displayed image is changed at a high speed. Describing problems in the high response speed LCD device with reference to FIGS. 1(A) and (B), the FIG. 1(A) shows a schematic configuration of a prior LCD device, which includes a LCD array 1, a data line drive circuit 2 and a gate line drive circuit 3. For example, the LCD array 1 has 640xc3x97480 pixels of VGA (Video Graphic Array) scheme. In this case, the data line drive circuit 2 supplies the image data to the 640 data lines connected to the 640 pixels of one pixel line, respectively, and the gate line drive circuit 3 sequentially supplies a gate pulse to the 480 gate lines. More particularly, when the data are written into a first pixel line along the gate line G1, the image data for the 640 pixels of the first pixel line stored in the data line drive circuit 2 are supplied to the data lines, and the gate line drive circuit 3 supplies the gate pulse to the gate line G1. The gate pulse turns on a thin film transistor of each pixel of the first pixel line, so that the image data are stored in a capacitor of each pixel formed by a pixel electrode, a liquid crystal layer and a common electrode, as well known in the art. When the data are written into a second pixel line along the gate line G2, the image data for the 640 pixels of the second pixel line stored in the data line drive circuit 2 are supplied to the data lines, and the gate line drive circuit 3 supplies the gate pulse to the gate line G2, and so on.
The FIG. 1(B) shows a timing diagram for sequentially supplying of the gate pulses to the 480 gate lines. During one frame period, the gate pulses are sequentially supplied to the 480 gate lines, so that the image data are sequentially written into the pixel lines during one frame period, as shown in the FIG. 1(B). A blanking period is provided between the adjacent two frame periods. The gate pulse has a width represented by a time period TA, which is represented by (the length of the frame period)/(the number of the gate lines). The time period TA is designed to turn on the thin film transistor of each pixel for sufficiently writing the image data into the capacitance of each pixel.
A problem in this scheme is that when the displayed image is changed for each frame period to display the motion picture, the displayed image of the one frame period remains in the human eyes as an afterimage and this afterimage overlaps with the display image of the next frame period, so that the image quality of the displayed image is degraded. FIG. 2 shows a timing diagram of a prior scheme for solving the problem of the afterimage caused in the scheme shown in the FIG. 1. One frame period is divided into a xc2xd frame period A and a xc2xd frame period B. During the first xc2xd frame period A, the 480 gate lines are sequentially activated to write the image data into all the pixel lines of the LCD array, and during the second xc2xd frame period B, the 480 gate lines are sequentially activated to write the black data into all the pixel lines of the LCD array. This operation can be performed by modifying the control scheme of the LCD device shown in the FIG. 1(A). Describing the write operation in the second xc2xd frame period B, when the black data are written into the first pixel line along the gate line G1, the black data for the 640 pixels of the first pixel line are stored in the data line drive circuit 2, and the gate line drive circuit 3 supplies the gate pulse to the gate line G1. The gate pulse turns on a thin film transistor of each pixel of the first pixel line, so that the black data are stored in the capacitance of each pixel. When the black data are written into the second pixel line along the gate line G2, the black data for the 640 pixels of the second pixel line are stored in the data line drive circuit 2, and the gate line drive circuit 3 supplies the gate pulse to the gate line G2, and so on. In this manner, the human eyes recognize the black image during the second xc2xd period B, and the afterimage of the image displayed in the first xc2xd period A is deleted from the human eyes during the xc2xd frame period B and is not overlap with the image of the next frame period. Although this scheme solves the problem of the afterimage, this scheme causes a new problem that the width of the gate pulse is reduced into TA/2, since the number of gate pulses twice as much as that of the FIG. 1(B) is required during one frame period, so that image data is not sufficiently written into the capacitance of the pixel, whereby the sufficient control of gray scale is not performed.
FIG. 3 shows a prior LCD device for solving the problem in the scheme shown in the FIG. 2. The LCD array is divided into a LCD array A which includes the gate lines G1 through G240 and a LCD array B which includes the gate lines G241 through G480, and the data line drive circuit 4 is used to supply the data to the LCD array A and the data line drive circuit 5 is used to supply the data to the LCD array B. The FIG. 3(B) shows a timing diagram of the operation of the LCD device. One frame period is divided into a xc2xd frame period A and a xc2xd frame period B. During the xc2xd frame period A of the first frame period, the 240 gate lines of the LCD array A are sequentially activated to write the image data into all the pixel lines of the LCD array A. During the xc2xd frame period B of the first frame period, the 240 gate lines of the LCD array A are sequentially activated to write the black data into all the pixel lines of the LCD array A, and the 240 gate lines of the LCD array B are sequentially activated to write the image data into all the pixel lines of the LCD array B. The black data for the LCD array B, into which the image data are written during the first frame period, are written in the xc2xd frame period A of the next frame period.
Since the LCD array is divided into the two halves, the write operation of the image data and the black data into the upper half A and the lower half B can be independently performed from each other, the width of the gate pulse can be maintained to the TA for sufficiently write the image data or the black data into the capacitance of each pixel, whereby this scheme solves the problem in the scheme shown in the FIG. 2. However, this scheme causes a new problem that this scheme requires the division of the LCD array into the two halves and the two data line drive circuits 4 and 5, so that the complicated control for supplying the data into the data line drive circuits 4 and 5 is required and the fabrication cost is increased.
Accordingly, it is an object of the present invention to provide the display apparatus which can prevent the display image from becoming unclear due to an overlap of the afterimage of the display image of the preceding frame period with the display image of the current frame period to improve the image quality of the motion picture, without requiring the division of the LCD array into the two halves and the two data line drive circuits.
In a first aspect of the present invention, a display apparatus in accordance with the present invention includes:
a display surface having a plurality of pixel lines; and a write circuit adapted to sequentially write an image into each of said plurality of pixel lines,
wherein said write circuit writes, during a time period for writing said image into at least one pixel line, a black color into another pixel line.
The another pixel line may be separated from the at least one pixel line by a predetermined distance.
The write circuit may write the black color into a plurality of pixel lines separated from the at least one gate line by the predetermined distance.
In a second aspect of the present invention, a display apparatus includes:
a display surface having a plurality of data lines arranged along one direction and a plurality of gate lines arranged along the other direction crossing the one direction, wherein one picture element is formed at each one of cross points of the data lines and the gate lines;
a data line drive circuit adapted to supply a data signal, which includes a black color signal portion and an image signal portion, to each of the plurality of data lines; and
a gate line drive circuit adapted to sequentially supply a gate pulse to each of the plurality of gate lines.
The gate line drive circuit supplies, during a write period for writing the data signal, a wide gate pulse, which gates both the black color signal portion and image signal portion of the data signal, to at least one gate line, and a narrow gate pulse, which gates the black color signal portion of the data signal, to another gate line.
The another gate line may be separated from the at least one gate line by a predetermined distance.
The black color signal portion may be included in a front portion of the data signal.
Preferably, the gate line drive circuit supplies the narrow gate pulse to a plurality of gate lines which are separated from the at least one gate line by the predetermined distance.
In a third aspect of the present invention a display apparatus includes:
a display surface having a plurality of data lines arranged in one direction and a plurality of gate lines arranged in the other direction crossing the one direction, wherein one picture element is formed at each of cross points of the data lines and the gate lines;
a data line drive circuit adapted to supply a data signal, which includes a black color signal portion and an image signal portion, to each of the plurality of data lines; and
a gate line drive circuit adapted to sequentially supply a gate pulse to each of the plurality of gate lines.
The gate line drive circuit supplies, during a write period for writing the data signal, a first gate pulse, which gates the image signal portion of the data signal, to at least one gate line, and a second gate pulse, which gates the black color signal portion of the data signal, to another gate line.
The image signal portion may be included in a front portion of the data signal.
In a fourth aspect of the present invention, a display apparatus in accordance with the present invention includes:
a display surface having a plurality of data lines arranged in one direction and Y gate lines arranged in the other direction crossing the one direction, wherein the Y is an integer equal to or larger than 1, one pixel is formed at each of cross points of the data lines and the gate lines, and a plurality of pixels along each of the Y gate lines form one pixel line;
a data line drive circuit for supplying a data signal, which includes a black color signal portion and an image signal portion, to each of the plurality of data lines; and
a gate line drive circuit for sequentially supplying a gate pulse to each of the Y gate lines.
The gate line drive circuit supplies, during a write period for writing the data signal, a wide gate pulse, which gates both the black color signal portion and image signal portion of the data signal, to at least one gate line, and a narrow gate pulse, which gates the black color signal portion of the data signal, to another gate line separated from the at least one gate line. The gate line drive circuit sequentially supplies the wide gate pulse to each of the Y gate lines during a frame period including a time periods T1 through TN, wherein the N is 1 through Y. One frame period and next frame period are separated by a blanking period. The black color signal portion is written, during the blanking period, into at least one pixel line which succeeds to the pixel line into which the black color is written during the last time period TN in the one frame.
Preferably, a polarity of the data signal supplied to each pixel line is alternately inverted in successive frame periods. The blanking period includes even time periods TB1 through TBE, each of which has a length equal to each of the time periods T1 through TN. The polarity of the data signal is adjusted, during the blanking period, to provide the data signal with a polarity which is opposite to that of the data signal supplied in a preceding frame period.
Still preferably, a polarity of the data signal supplied to each pixel line is alternately inverted in successive frame periods. The blanking period includes odd time periods TB1 through TBO each of which has a length equal to each of the time periods T1 through TN. The black color signal portion is written, during the blanking period, into the pixel lines equal to the number of the odd time periods TB1 through TBO during the blanking period.
The present invention realizes the display apparatus which can prevent the display image from becoming unclear due to an overlap of the afterimage of the display image of the preceding frame period with the display image of the current frame period to improve the image quality of the motion picture, without requiring the division of the LCD array into the two halves and the two data line drive circuits.